1. Field of the Invention
The present invention relates to a semiconductor device including a transistor that has a HKMG structure.
2. Description of the Related Art
In a metal-insulator-semiconductor field-effect transistor (MISFET) that has a gate insulating film and a gate electrode formed on the gate insulating film, it has been a common practice to use a silicon oxide film, SiO2 in this case, as the gate insulating film and a polysilicon film as the gate electrode.
Recently, the thickness of gate insulating film has been further reduced with miniaturization of MISFETs. One problem of a thinner gate insulating film is the relative increase in the strength of the electric field on the gate electrode, and is occurrence of depletion of the gate electrode composed of polysilicon. Another problem of a thinner gate insulating film is occurrence of the so-called tunnel current caused by electrons, which would flow through a channel, tunneling a bather formed by the silicon oxide film so as to flow through the gate electrode.
JP2007-329237A and JP2006-024594A disclose MISFETs that have a high dielectric constant gate insulating film (high-k insulating film) composed of a high dielectric constant material, the dielectric constant of which is higher than SiO2, and a metal gate electrode composed of a metallic material. In the MISFETs, the metal gate electrode can prevent the depletion of the gate electrode, and the high-k insulating film can prevent the occurrence of tunnel current. An MISFET that has a high-k insulating film and a metal gate electrode is referred to as an MISFET that has a HKMG structure.
Description will now be made of a process of forming first and second MISFETs that have a HKMG structure and different threshold voltages on a semiconductor substrate. It is noted that the first MISFET is formed in a first region and the second MISFET is formed in a second region adjacent to the first region on the semiconductor substrate.
First, a high-k insulating film is deposited, and then an electrode material for a metal gate electrode of the first MISFET is deposited. The deposited electrode material is removed in all regions except for the first region. A first gate stack layer (first GS layer) in which the high-k insulating film and the electrode material for the metal gate electrode of the first MISFET are layered is thus formed in the first region.
Next, an electrode material for a metal gate electrode of the second MISFET is deposited, and then the deposited electrode material is removed in all regions except for the second region. A second gate stack layer (second GS layer) in which the high-k insulating film and the electrode material for the metal gate electrode of the second MISFET are layered is thus formed in the second region. Thereafter, the first and second GS layers are subject to gate processing, such as etching, to turn the layers into gates of the MISFETs.
The present inventor has now discovered a problem in which a residue of a GS layer is generated during the gate processing and the residue may cause short circuit lines.
In general, the electrode material for the metal gate electrode of the first MISFET deposited in all regions except for the first region is removed by wet etching in order to prevent damage to the high-k insulating film. At this time, wet etching may etch away electrode material included in a part of the first region, where the electrode material included in the part of the first region is carved to create an overhang portion. In the case where an overhang portion is generated, the electrode material for the metal gate electrode of the second MISFET may be trapped under the overhang portion. The electrode material trapped under the overhang portion impedes etching in the gate processing, and generates a residue of a GS layer on the border between the first region and the second region. The residue is conductive because the residue contains the electrode material for the metal gate electrode. Consequently, the residue causes a short circuit when the residue is in contact with two lines having different potentials.